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MMC Hardware

MMC Interface Hardware Details

The interface is a simple one with a single byte location used as the data port and one byte used for the control register.

Data register:  Allows a single byte to be written or read from the MMC.  Bytes that are written to this location are sent to the card at the clock speed selected from the Control register.  Bytes read from this location are always one transfer old.  Regardless of speed selected the time to transfer a single byte is greater than the cycle time for a read in the bus of the color computer.  When data is read from the card the write data line is held high sending an effective value of 255 to the write pin of the MMC.

Control register: Allows control of MMC clock and CS assertion
Bits
7
6
5
4
3
2
1
0

SPD
N/U
N/U
N/U
N/U
N/U
CS1
CS0

Bit 7: clock speed bit. Bit set is slow speed, bit cleared is fast speed bit.  Clock is either Color computer Clock E / 8 (1.78Mhz/8 or .89Mhz/8)  or E&Q combined to achieve a double rate clock of 1.78Mhz*2 at high speed or .89Mhz*2 at low speed.  
Bits 6-2: Not used.  Reserved for future use
Bit 1: CS for MMC #2  Bit set will select card number 2 and bit cleared will deselect card #2.
Bit 0: CS for MMC #1  Bit set will select card number 1 and bit cleared will deselect card #1.

Prototype Design

First implementation was to use discrete logic (which was a complete failure).  After trying some simple logic designs with Atmel's free FPGA software I decided to give programmable logic a try and purchased the evaluation kit.
The choice to use the Atmel AT1508 FPGA was based on cost.  I was able to purchase an evaluation kit from DigiKey for less than $100.  Aproxametly 50% of the logic within the FPGA was used and there are still many unused I/O pins available for future use.
Use of the 74LVC245 was required to reliably level shift the MMC clock and data pins from 5.0v to 3.3v.  I tried other options such as mosfets and transistors, but I was unable to get them to ramp up in speed to E clock (even at slow speed .89Mhz).  

During development I created a few prototype boards the first was an attempt to use discrete logic.


The second board almost worked, however several tries at converting the logic levels from 3.3v to 5v caused me to create a third board.


The third and final prototype worked with little effort (after the CPLD logic was correct!)
 
 

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COCOMMC.PLD
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Jim Hathaway,
Mar 12, 2009, 8:53 PM
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Jim Hathaway,
Mar 12, 2009, 7:10 PM
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Jim Hathaway,
Mar 12, 2009, 7:11 PM
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Jim Hathaway,
Mar 12, 2009, 6:57 PM
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Jim Hathaway,
Mar 12, 2009, 7:11 PM
Ĉ
Jim Hathaway,
Mar 12, 2009, 7:11 PM
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Jim Hathaway,
Mar 12, 2009, 6:57 PM
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