Hardware Design


The timing was the most frustrating part of the project. Just when it looked like the interface should have worked, it did not. In general there are seven major control lines that an IDE device needs satisfied for a given cycle. First there is the read and write lines (RIO/WIO). These pins work by both staying in a logic high state until ether condition is required (read or write to a device register). The next group of pins (CS0 and CS1) are used to determine the block of registers selected. We only use one block for the interface, so when a register is written/read to, the CS0 pin drops to a logic low level. The address lines A0-A2 along with CS0 and CS1 are sent through a 74HCT574 latch that is triggered by the change of state of the Q clock sent from the COCO. The output of this latch is always in the 'on' state making the last signals sent to the drive stay active until another read/write action. The main function of the latch is to make all the control lines (A0-A2, CS0-CS1) change state at the same time. Without the latch data transfers could have random failures- I know, I saw many of them! The Read and Write lines to the drive change state at the rise of E to allow the A0-A2, CS0, CS1 control lines to change their state and give a small delay before we tell the drive to read or write to the selected drive. Below is a table showing a timing example for the IDE interface:

Below is a simple Schematic of my original design: